Component or module packages using a column grid array (CGA), ball grid array (BGA) or chip scale package (CSP) may use various module processing technologies to achieve higher lead pin densities, that range from 0.050 in. (1.27 mm) pitch to less than 0.025 in. (0.63 mm) pitch. However, for connection of area array modules having array pitches of less than 1 mm, circuit board fabrication is both difficult and expensive. Fabrication restrictions arise because minimum plated through hole (PTH) sizes, internal plane registrations, and minimum line and space needs to support wiring densities that enable module interconnect and wiring redistribution exceed technological process limits of conventional printed circuit board (PCB) manufacture. Although several methods exist which enable generation of boards that support high density module interconnects including additive plating methods, plasma and/or laser via fabrication methods, and use of high density patch interconnects, most processing and packaging techniques are either still very expensive, are currently in exploratory stages of development, or do not support high volume production requirements.
Printed circuit boards are commonly fabricated using plated through via holes that extend through the board and which are plated to present a via capture pad surrounding the opening at least one end and a coating on the via hole cylindrical surface which communicates with the opposite side of the board. The via capture pad surrounding the via termination affords a "via-in-pad" design. The via hole plating also contacts the land surfaces on intermediate layer surfaces that are meant to communicate with the contact associated with the via.
To optimize the density of module interconnections, it is necessary to effect connection between the terminals of a module and the printed circuit board plated via capture pads that surround the via openings. Such a connection requires the formation of multiple reliable solder connections at the ends of the aligned via openings. The solder applied to the confronting end of the plated flange at the via opening tends to flow into the via passageway when heat is applied to effect module connection. The solder that remains at the connection site is then less than required to effect a reliable electrical connection.
The problem of reliable pad-on-via solder connections of modules to printed circuit boards has been addressed by prior art processes. A method for resolving the problem is to sequentially apply solder paste and reflow the material until the via hole is prefilled and wicking of solder away from the attachment site during solder reflow has ceased. Such a method is illustrated by the teaching of U.S. Pat. No. 5,275,330 issued to Isaacs et al, where the via passage is filled with solder prior to the solder ball pad-on-via connection of an electronic module. By using this card design and assembly process approach, the lead density can be increased from 0.050 in. to an effective pitch of 0.025 in. or less. Since this is an area measurement, this improvement constitutes a four times increase in local wiring density using common PCB fabrication technology. Although the process of the patent can be successfully used for assembly, multiple pass solder plugging steps are required and the process may encounter less than acceptable assembly yield for high volume production. Yield detractors are primarily caused by surface tension variability of the solder within discrete vias coupled with remelting events during component attach. In some vias, solder does not remain in place to provide an adequate solder plug and joint inconsistencies such as opens and insufficient solder joint fillet formations may result after assembly.